The Design of ASIC for Image Processing of 3D Color Scanner
Abstract
The 3D color information acquisition system can obtain the coordinate and color information of the object surface in the 3D space. It is important for computer vision and one of the research focuses in information technology and it is widely applied in areas such as industry manufacture, film, TV and virtual reality, etc. The new real time reconfigurable 3D laser colour information acquisition system adopting master-slave system architecture using parallel processing technology,fast algorithms and ASIC which made by FPGA has been developed to overcome the problems of the former 3D laser color scanner (3DLCS). It can accomplish important image processing fast algorithms by slave system based on FPGA. Then the important information is sent into host computer through PCI interface to accomplish advanced image processing, 3D reconstruction and 3D modeling. The new 3D information acquisition system can acquire 3D and colour information of object in real time and the 3D images are displayed promptly on the screen of host computer. The system performance is improved greatly and the devices are low cost. In addition, it has good security and can implement special function and is applicable to many special cases. A patent is applying for the real time reconfigurable 3D scanner.
Multipliers are one of the important components in digital signal processing. It is applied to the chip of digital signal processing, especially digital image processing. The parallel multiplier designed by us is used as a high-speed unit for the image processing ASIC of real time 3D scanner. The usual design methods of multiplier are summarized. A 15 bit parallel high-speed multiplier based on Wallace tree is implemented in EP1K50 so that high accurate matrix computing can be accomplished in a chip for 3D scanner. High-speed multiplier is very important for the development of the real time reconfigurable 3DLCS, especially to make 3D scanner into SOC in the future.
A video image-processing special integrate circuit for the real time 3D scanner is developed, which possess of independence knowledge property right by us. The ASIC is the system core for implementation of the key fast algorithms. The algorithms of extracting central line of laser stripe, head contour and central colour line from video image are accomplished by FPGA processor, which is made of EPEK50. In addition, the ASIC must do control function that includes data lock module, I/O control module for FIFO and other signal control modules that is required by system. The data lock module can translate the video capture port signal into true colour RGB signal. An interactive fast algorithm of extracting the head contour has been proposed for real-time image processing, which is accomplished by FPGA processor and host computer together. The development of ASIC is the most important to the whole system.
Key words:3D information acquisition FPGA fast algorithm ASIC Multiplier design