The hardware design of the PLL experimental platform based on MCU
Abstract: In order to ensure the stabilization and reliability of the communications, the modern communication systems have offered high requirements on the accuracy and stabilization in the frequency of communication equipment. Though the signal of RC or LC is adjusted conveniently, it is not steady enough. Also, the quartz crystals oscillator has a high stabilization, but the its frequency adjustment range is not enough. Using the technology of modern PLL Frequency Synthesizer, it can bring the frequency adjustment range up to the required standard and its stabilization is high enough. The technology of the modern PLL Frequency Synthesizer, takes an important part in present and future field of communication.
PLL is made up of phase detector, loop filter and voltage control oscillator. Phase detector is used by detecting the direct phase separation of the two input signals. In this design, the phase comparator and the voltage control oscillator VCO comprise PLL LM4046. 1/N scale down circuit is a three-grade frequency divider and each grade uses BCD code synchronous and 1/N counter MC14522. The input frequency of each grade gauges the initialized data base to its counter in the form of 8421BCD code, by using four small toggle switches. The optional scope of the input frequency is 0-999. When inputting the external signal generator, it received the oscillator frequency under the circuit feedback, the circuit is on the locked status, the oscillator frequency of VCO equals to N. With the changing of the input frequency N, the oscillator frequency of VCO is changing too. This is the process of frequency synthetic.
KeyWords: PLL , frequency Synthesizer, frequency dividing ratio
.
