The subject of this graduation project is that “The design of interleavingcoder with FPGA”, In view of the accept data error of figure communication system which bring about in transmission process.We discuss the data recording method,These data get change through the interleaving matrix. Mainly examine our information theory and coding, the situation in respects such as digital circuit design and programming ability, etc. Observe and analyze design circuit ability, and actual programming ability independently. And the broad application of interleaingcoder in the practical communication system.
This subject is mainly discussing the circuit realizing of interleavingcoder with shift register. Under Max+ PlusⅡ software roof garden,We apply the embedded dual port memory of FPGA device and macro model black through VHDL program design to realize interleavingcoder. It can decrease error code rat,increase the communication efficiency,with the interleaving technique.