摘 要
本设计运用VHDL语言，采用Top To Down的方法，设计了一种8位简易的数字频率计，并利用Isp Expert集成开发环境进行编辑、综合、波形仿真，并下载到CPLD器件中，经实际电路测试，该系统系统性能可靠。主要功能有：频率测量、周期测量和脉冲宽度测量。整个设计可以分为三个部分：方案设计、软件设计、硬件设计。本文详细介绍了简易数字频率计的软件设计和硬件设计。
关键词：EDA；VHDL；数字频率计；波形仿真；CPLD
Abstract
The use of VHDL design language, the use of Top To Down approach, designed a simple 8-bit digital frequency meter, and the use of Isp Expert integrated development environment for editing, synthesis, simulation waveforms, and downloaded to the CPLD devices, the actual circuit test, the system reliable system performance. The main features are: the frequency of measurements, the cycle measurement and pulse width measurement. The whole design can be divided into three parts: program design, software design, hardware design. This paper describes a simple digital frequency of software design and hardware design.
Key word: EDA；VHDL；digital frequency meter；Waveform Simulation；CPLD
