ABSTRACT: The design of ASIC (Application of Specified Integrated Circuit) for image processing is the subsystem of the system with 3D laser color scanner.
In the following system we will use FPGA (Field Programmable Gate Array) to perform high-speed parrel multiplier(adds, subtracts, multiply, divide) and connect all the control module in order to gain three threads of image. Among them algorithm partly includes to be drawn laser thread module、calculation contour module and takes the center color thread module; Controlling parts include changing VPO's video output port signal to RGB really data latch modules of colored signal. and slow input/output control and the signal that some other systems need depositing the ware of each FIFO . To meet the guaranty speed requirement, All modules are controlled by using the synchronous clock. The synchronous clock uses LLC2's signal giving rise to by video frequency processor SAA7111's analog-digital conversion ware.
Using the programmable logic of the Max+plusII of Altera corporation to realize the simulation and analysis of signal for the system.
Keywords：ASIC FPGA Reconfigurable in the real time
