关键词: 参数测量 运算放大器 DDS FPGA SPCE061A 数字信号处理
Abstract: In light of this system on-chip system design architecture, using a combination of FPGA and SPCE061A ways to SPCE061A SCM process control and task scheduling for the core; FPGA as an external expansion, internal self-built system bus, the address decoding all-Decoding. FPGA internal built DDS controller, microcontroller through the system bus to the provisions of the storage unit into the sine table; then DDS controller to set the frequency, auto-loop scanning, generating high-precision, high stability, 5Hz baseline measurement signal. Sweep the signal through the FPGA system clock 30MHz sub-band and the external phase-locked loop (FPGA using FLEX10K10 not have an internal phase-locked loop) frequency doubling, resulting in a high frequency stability, amplitude stability of the sweep signal. Amplifier parameter measurement reference GB3442-82 standard, low-frequency signal amplitude measurements taken by AD high-speed sampling, and then digital processing methods; high-frequency signals using an integrated RMS magnitude of the direct conversion chip measured. A / D converter uses the internal SPCE061A native 10-bit AD. Main achieved SPCE061A User Interface (Keyboard scanning, LCD display, data printing and other services to the process of scheduling), AD conversion, and measured parameters (Vio Iio Kcmr Avd BWG Tr) calculated with the host computer communication, etc. functions. Host machine is mainly send the measure to achieve the down-bit machine instructions, and the next crew exchange of measurement data, and data storage, playback, statistics.