摘要:
MC88920时钟脉冲驱动器利用相位锁存器技术锁定偏移输出频率且相位输入在基准值时钟之上。它用于复杂指令集计算机微处理器或者单处理机简化指令系统计算机系统的时钟分布。复位输入/复位输出(锁定)引脚具有处理器复位功能设计具体地说对MC68 / E / LC030 / 040微处理机系列。PLL允许强电流、低偏移输出到锁定单个时钟输入并且分配多单元零延迟。PLL同样地允许MC88920增加低频输入时钟并且分配较高(2X)系统频率。全部的输出功率具备±36mA驱动(等同高和底电平)CMOS电平。可以驱动CMOS和TTL输入电路,全部的输入端与TTL兼容.
Abstract:The MC88920 Clock Driver utilizes phase–locked loop technologylock its low skew outputs’ frequency and phase onto an input referenceclock. It is designed to provide clock distribution for CISC microprocessoror single processor RISC systems. The RST_IN/RST_OUT(LOCK) pinsprovide a processor reset function designed specifically forMC68/EC/LC030/040 microprocessor family.The PLL allows the the high current, low skew outputs to lock ontosingle clock input and distribute it with essentially zero delay to multiplelocations on a board. The PLL also allows the MC88920 to multiply a
frequency input clock and distribute it locally at a higher (2X) systemfrequency. Can Drive Either CMOS or TTL Inputs. All Inputs AreTTL–Level Compatible