Abstract：
The MPC9992 is a 3.3 V compatible, PLL based PECL clock driver. Using SiGe technology and a fully differential design ensures optimum skew and PLL jitter performance. The performance of the MPC9992 makes the device ideal for workstation, mainframe computer and telecommunication applications. With output frequencies up to 400 MHz and output skews less than 100 ps the device meets the needs of the most demanding clock applications.
The MPC9992 offers a differential PECL input and a crystal oscillator interface. All control signals are LVCMOS compatible.
The MPC9992 has a system synchronization pulse output QSYNC. In configurations with the output frequency relationships are not integer multiples of each other QSYNC .provides a signal for system synchronization purposes.
The MPC9992 is a mixed analog ital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins.
