Along with the rapid development of electronic design technology, special integrated circuit ASIC and CPLD (Complex Programmable Logic Device) need complexity higher. The digital circuit and the system complex degree of the digital communication, the industrial automation control and so on also need higher. The topic of my graduated paper is the multi-channel JTAG downloading device design. Not only I must understand the disposition of CPLD downloading line, but also I must be familiar with the programmable logic chip.
The first part, a simple introduce of VHDL, which is a kind of hardware described language. In this part, I lead a basic view of VHDL and show how to use it to design the circuit. A simple introduction of MAXPLUS2 which is a software to modulate the program of the VHDL is the next one, and I also introduce how to design it. Next part is how to make hardware PCB electric circuit. I elaborate CPLD (Complex Programmable Logic Device) internal structure and the development, as well as CPLD convention design flow and method. In the fifth part, that is the main part of my paper. I write something about the work pattern of Byte blaster downloading line and the internal structure of programmable logic chip 7128. I also give my aim and process of design and introduce my principle of design. In the last part of my main paper, I write down a lot of my feelings and opinions which generated from the last three month, from my learning and experiment. That is the most important part of paper, as in the part I narrate many problems happened in my design and at last how I solved. From this graduation design, I have learnt a lot of actual knowledge, and studied many methods as well as how to think about tacking problems. I am very grateful for my classmates and teachers who have offered me much help.
